Fujitsu MB86R02 Jade-D Hardware Manual page 459

MB86R02 'Jade-D' Hardware Manual V1.64
DLS (Display Layer Select)
Register
DisplayBaseAddress + 0x180
address
Bit number
31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
Reserved
R/W
Initial value
This register defines the blending sequence.
Bit 3 to 0 DSL0 (Display Layer Select 0)
Selects the top layer subjected to blending.
0000
0001
:
0101
0110
:
0110
0111
Bit 7 to 4 DSL1 (Display Layer Select 1)
Selects the second layer subjected to blending. The bit values are the same as DSL0.
Bit 11 to 8 DSL2 (Display Layer Select 2)
Selects the third layer subjected to blending. The bit values are the same as DSL0.
Bit 15 to 12 DSL3 (Display Layer Select 3)
Selects the fourth layer subjected to blending. The bit values are the same as DSL0.
Bit 19 to 16 DSL4 (Display Layer Select 4)
Selects the fifth layer subjected to blending. The bit values are the same as DSL0.
Bit 23 to 20 DSL5 (Display Layer Select 5)
Selects the bottom layer subjected to blending. The bit values are the same as DSL0.
DLS5
RW0 RW
R0 R0
0 0 101 0
L0 layer
L1 layer
:
L5 layer
Reserved
:
Reserved
Not selected
DLS4 DLS3 DLS2
RW RW RW
R0 R0
100 0 011 0 010
DLS1 DSL0
RW RW
R0 R0
0 001 0 000
18-101