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MB86R02 'Jade-D' Hardware Manual V1.64
L1ETC (L1 layer Extend Transparency Control)
Register
DisplayBaseAddress + 0x1A4
address
Bit number
31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
L1ETZ
R/W
RW
Initial value
This register sets the transparent color for the L1 layer. When L1ETC = 0 and L1EZT = 0, color 0 is
displayed in black (transparent).
For YCbCr display, transparent color checking is not performed; processing is always performed
assuming that transparent color is not used.
Bit 23 to 0
L1ETC (L1 layer Extend Transparent Color)
Sets transparent color code for the L1 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 31
L1EZT (L1 layer Extend Zero Transparency)
Sets handling of color code 0 in L1 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
L2ETC (L2 layer Extend Transparency Control)
Register
DisplayBaseAddress + 0x1A8
address
Bit number
31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
L2ETZ
R/W
RW
Initial value
This register sets the transparent color for the L2 layer. The 24 bits/pixel transparent color is set
using this register. The lower 15 bits of this register are physically the same as L2TC. Also, L2ETZ
is physically the same as L2TZ.
When L2ETC = 0 and L2EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0
L2ETC (L2 layer Extend Transparent Color)
Sets transparent color code for the L2 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 31
L2EZT (L2 layer Extend Zero Transparency)
Sets handling of color code 0 in L2 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
Reserved
R0
Reserved
R0
L1TEC
RW
L2TEC
RW
18-111
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