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MB86R02 'Jade-D' Hardware Manual V1.64
Function
Built-in SRAM
DMAC
Timer
GPIO(*2)
PWM(*2)
ADC
GDC (*1)
APIX
I2S (*2)
UART (*2)
I2C
SPI (*2)
Embedded general purpose SRAM 32KB × 2 (32 bit bus)
AHB connection × 8ch
Transfer mode: Block, burst, and demand
32/16 bit programmable × 2 channels
Max. 24 usable channels
Interrupt function
8 channels
Duty ratio and phase are configurable
10 bit successive approximation type A/D converter × 4ch
Sampling rate: 648KS/s (max. sampling plate)
Nonlinearity error: ± 2.0LSB (max.)
Display controller
RGB666 or RGB888 output
Max. 6 layered display
Max. 2 screen output (RGB)
Digital video capture function
Max. 2 inputs: ITU656 or RGB + ITU656
Geometry engine (MB86296 compatible display list is usable)
2D/3D drawing function (MB86296 compatible display list is usable)
Remote Handler 2ch, Master or Slave functionality
Audio output/ input × 1ch (L/R)
Supported three-wire serial (I2S, MSB-Justified) and serial PCM data transfer interface
Master/Slave operations are selectable
Resolution capability: Max. 32 bit/sample
Max. 6 channels (dedicated channel: 6ch)
1 channel: capable of input/output CTS/RTS signals
8 bit pre-scaler for baud rate clock generation
Enabled DMA transfer
3.3V pin × 2ch
Supported standard mode (max. 100kbps)/high-speed mode (max. 400kbps)
× 2ch
Full duplex/Synchronous transmission
Transfer data length: 1 bit unit (max. 32 bit) (programmable setting)
The length of the SPI interface packets is variable to permit the use of variable length
addresses and data accesses
Supports writes/reads to the internal module connected to the AHB (variable, from 1 to 16
bytes)
Conforms to Freescale Semiconductor's advocacy SPI (CPOL=0, CPHA=0)
Corresponds to the speed of general purpose CPUs (set the frequency of SPICLK to 1/2 or
less of the HCLK frequency)
Host CPU handshaking communication makes software flow control possible
The MB86R02 can only operate in slave mode whereas the host CPU is the bus master
The packet sizes must be in 8 bit units
No CRC error detection functionality.
No automatic procedure for resends in the case of errors (no ARQ functionality)
Supported burst transfer modes for the AHB are single, incr or incr4
Correct operation cannot be guaranteed if simultaneous access to the module occurs from
the APIX-LINK unit
Outline
1-7
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