Fujitsu MB86R02 Jade-D Hardware Manual page 88

MB86R02 'Jade-D' Hardware Manual V1.64
CCLK
For each divider Lx is {1, 2, 4, 8, 16}
PLLCLKM
5-8
ARMADM[2:0]
DIV
1/L
X
ARMBDM[2:0] STOP | ARMBGATE[0]
DIV
1/L
X
Figure 5-4 Clock Structure, ARM clocks
Figure 5-5 Clock structure, DCLK
STOP | ARMAGATE[0]
Gate
Gate
CCLK_O
Used for DCLK
ARMA_O
Used for ARM & DDR IF
ARMB_O
(ETMclock)