Supply Clock; Registers - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
32.3

Supply clock

The AHB clock signal is supplied to the MediaLB interface module. Please refer to "5. Clock reset
generator (CRG)" for information about setting the frequency and the control specifications of the
AHB clock.
32.4

Registers

The registers of this GDC are mapped in byte addresses (8 bit), however local addresses of the
MediaLB module are accessed using word addresses (32 bit).
Register address
FFF6_0000h
FFF6_0004h
FFF6_0008h
...
32-2
MediaLB local address
00h
01h
02h
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