Outline Of Each Functional Block - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
Figure 1-2 MB86R02 'Jade-D' DPERI_TOP (Display Peripherals) Detail Diagram

1.2.1 Outline of each functional block

CPU core (333 MHz)
The CPU block is an ARM926EJ-S core which is connected to each I/O via the internal AHB3
bus. It has a Harvard architecture with separate instruction (I) and Data (D) caches and memory
and additionally incorporates a JTAG interface for debugging and running a boundary scan.
GDC core
The GDC core consists of a MB86296 'Coral PA' compatible graphics controller core with two
display and capture units. The core has two functional modes:

AHB slave functionality, making it possible to write display lists using the CPU core or the
DMA controller as a master, and

AXI master functionality which enables the reading of display lists saved in DDR2 memory,
whereby the GDC acts as the master
AXI bus (64 bit/166 MHz)
This bus provides a bridge between external DDR2 main memory and chip-internal resources.
The following 4 bus masters are connected to the AXI bus:
1-4