Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
11.6.3 SRAM/Flash area register 0/2/4 (MCFAREA0/2/4)
Register address
Bit No.
31
Bit field name
R/W
Initial value
Bit No.
15
Bit field name
R/W
Initial value
Bit31-23: Reserved
Reserved bits.
Write "0" to these bits. Their read value is undefined.
Bit22-16: MASK (Address mask)
These bits set mask value of the one set to ADDR. This external bus interface masks
ADDR (masked with setting "1") and internal bus mask address according to the
specified mask to compare them. When they are matched, external bus interface
accesses to MEM_XCS[4/2/0] signal. [22:16] masks each address [26:20].
(Example)
ADDR = 00001000 (b)
MASK = 0000011 (b)
<When the device is selected>
Internal bus address (external interface address): AD = 0x10900000
Mask
ADDR & (!MASK)
AD [27:20] & (!MASK)
device is selected
<When the device is not selected>
Internal bus address (external interface address): AD = 0x10c00000
Masking
ADDR & (!MASK)
AD [27:20] & (!MASK)
is not selected
The masking selects area size; in this example, 0x10800000 - 0x10b00000 (4MB)
are selected. The bit specified "1" with masking is lost during mask processing.
These bits are invalid even if they are set to ADDR. When LSB in the example is
1 (ADDR = 00001001 (b)), the same address field is selected since it is invalid in
masking. The correlation of the size in mask setting and address field is shown
below.
0000000 (b) → 1MB
0000001 (b) → 2MB
11-8
BaseAddress + 0x0040(MEM_XCS[0]),
BaseAddress + 0x0048(MEM_XCS[2]),
BaseAddress + 0x0050(MEM_XCS[4])
30
29
28
27
26
Reserved
R/W0
X
14
13
12
11
10
Reserved
R/W0
X
= 00001000 (b)
= 00001000 (b)
25
24
23
22
21
9
8
7
6
5
(in order of MEM_XCS[0/2/4]) 64,32,0
= 00001000 (b) ..... Matched, and this
= 00001100 (b) ..... Unmatched, and device
0001111 (b) → 16MB
0011111 (b) → 32MB
20
19
18
17
16
MASK
R/W
15 (16MB width)
4
3
2
1
0
ADDR
R/W
Advertisement
Table of Contents
