Exirc Signal Timing - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
34.5.17

EXIRC Signal Timing

Table 34-45 AC Timing
Signal Name Symbol
t
INT_A[3:0]
dw
The case that external interrupt input request is edge (rising edge and falling edge), input data width (tdw) is
regulated as follows. When level ("H" or "L") is selected as the request, it should be held until interrupt
process is completed.
A indicates APB bus clock cycle.
APB BUS CLK
INT_A[3:0]
Figure 34-41 EXIRC Timing
Description
Input data-width
t
dw
Value
Min. Typ. Max.
A – –
Unit
ns
34-47