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MB86R02 'Jade-D' Hardware Manual V1.64
Write "0005" to DRIC1 register (offset + 02h)
Write "0044" to DRIC2 register (offset + 04h)
Write "C001" to DRIC register (offset + 00h)
Write "0032" to DRCM register (offset + 08h)
Write "3318" to DRCST1 register (offset + 0Ah)
Write "6E32" to DRCST2 register (offset + 0Ch)
Write "0141" to DRCR register (offset + 0Eh)
Write "0002" to DRCF register (offset + 20h)
Write "0001" to DRASR register (offset + 30h)
13-32
A
Continued from the previous page
END
DDR2 IF: Issue EMR (1) command
Set to ODT 50Ω
DDR2 IF timing setting (BT, AL, CL, and BL)
DDR2 IF timing setting (tRCD, tRAS, tRP, and
DDR2 IF timing setting (tRFC, tRRD, and tWR)
Refresh issued at DDR2C normal operation mode
Command issuing interval setting (the value is
f
)
Address FIFO's number of stage setting in DDR2C
(set to 8 stages)
DDR2C's AXI cache function setting on
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