Sub Frame Construction - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
27.7.3.2

2 sub frame construction

I2S_SCKx
1 bit
I2S_WSx (FSLN = 0)
I2S_WSx (FSLN = 1) 0-1 bit
I2S_SDIx/SDOx
Channel-0 (7-32 bit)
of sub frame #0
Description
1. When SBFN bit of CNTREG register is "1", frame becomes 2 sub frame composite that first
sub frame is 0 and the next one is 1.
2. Set number of channel of sub frame 0 to S0CHN of MC0REG register, and set number of
sub frame 1 channel to S1CHN of the register. Those numbers of channel are individual
that they do not need to have the same channel. Up to 32 channels are settable.
3. Channel bit length (word length) of sub frame 0 is determined by S0WDL of MC0REG
register. For sub frame 1, they are determined by S1WDL of MC0REG register. Since
channel bit length of the sub frame is individual, those channels (word length) do not need to
be the same.
4. Sub frame channel starts from 0th. Each channel of sub frame 0 is settable to valid/invalid
with the corresponding bit of MC1REG register, and corresponding bit of MC2REG register
for sub frame 1.
Transmission/Reception of data is not performed to invalid channel.
5 Dummy bit can be inserted behind sub frame 1 by setting OVHD of CNTREG.
0-1023 bit are insertable.
6. Polarity of I2S_WSx is set to FSPL bit of CNTREG register.
7. Pulse width of I2S_WSx can be set to 1 bit or 1 channel length by setting FSLN bit of
CNTREG register.
Channel length setting of 1 channel is determined by the channel length of sub frame 0.
8. Timing from the edge I2S_WSx becomes valid to the first bit of frame is settable to "0" or "1"
bit.
27-30
Channel-0 (7-32 bit)
Channel-n (7-32 bit)
of sub frame #0
Sub frame #0 (1-32 channels)
One frame with two sub frames
Figure 27-3 2 sub frame composite frame
Channel-n (7-32 bit)
of sub frame #1
of sub frame #1
Sub frame #1 (1-32 channels)
Over-head
(0-1023 bit)