Fujitsu MB86R02 Jade-D Hardware Manual page 656

MB86R02 'Jade-D' Hardware Manual V1.64
R/W
Reset
value
Sync mixer 11 signal selection
Bit 14 - 12 SMX11SIGS_S4
select 4 000b=const zero,001b=sync sequencer output, 010b...111b sync pulse generator output
Bit 11 - 9 SMX11SIGS_S3
select 3
Bit 8 - 6 SMX11SIGS_S2
select 2
Bit 5 - 3 SMX11SIGS_S1
select 1
Bit 2 - 0 SMX11SIGS_S0
select 0
DIR_SMx11FctTable
Register address BaseAddress + 524
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Sync mixer output = function table [a] a = s4*24+s3*23+s2*22+s1*21+s0*20
Bit 31 - 0 SMXFCT11
Sync mixer 0 function table
DIR_SSwitch
Register address BaseAddress + 528
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
Field name
R/W
Reset value
Sync switch
Bit 13 InvCtrEn
Enable for inversion control: 0b=disabled, 1b=enabled
Bit 12 - 0 SSWITCH
Delay selection for all TSIG outputs including inversion control (bit 12) (0=none, 1=0.5 cycle delay of pixel clock)
DIR_RBM_CTRL
Register address BaseAddress + 52C
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Field name
R/W
Reset value
RSDS Bitmap Control
Bit 10 ColOrder
- 8 Color Component Ordering: 000b=RGB, 001b=BRG 010b=GBR 011b=RBG 100b=GRB 101b=BGR 110b=reserved 111b=reserved
Bit 5 BitOrder
Bit Order Inversion: 0b=normal order (MSB 7 downto 0), 1b=inverted order (0 upto 7 MSB)
Bit 4 swapoddevenbit
ES1: Reserved, ES2: This field has only effect for ES2 and later: swap odd and even bits, 0b=no change, 1b=bit 6 and 7, 4 and 5, 2
and 3, 0 and 1 are swapped, This is needed for RSDS channel order inversion
Bit 3 BitPerCol
Bits per Colour: 0b=6bits (2 LSBs are set to '0'), 1b=8bits
Bit 2 - IfcType
1 Interface protocol type: 00b=TTL, 01b=RSDS, 10b,11b=reserved
Bit 0 Bypass
Bypass module: 0b=bypass disable, 1b=bypass enable
DIR_PIN0_CTRL
Register
BaseAddress + 534
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
22-22
RW
0
H
H
H
H
19 18 17 16 15
NChanSel0 ChanSel0
RW RW
0 0
H H
RW RW
0 0
H H
SMXFCT11
RW
FFFFFFFF
H
13
InvCtrEn
RW
0
H
5
ColOrder BitOrder swapoddevenbit BitPerCol IfcType Bypass
RW RW
0 0
H H
14 13 12 11 10 9 8 7
NDelay0 Delay0 InOut0 NPolarity0 Polarity0 Mode0
RW RW RW
0 0 0
H H H
RW RW
0 0
H H
12 11 10 9 8 7 6 5 4 3 2 1 0
SSWITCH
RW
0
H
4 3 2 1 0
RW RW RW RW
0 0 0 1
H H H H
6 5 4 3 2 1
Boost0
RW RW RW RW
0 0 1 0
H H H H
0