MB86R02 'Jade-D' Hardware Manual V1.64
15.7.4 Retry, split, and error
The DMAC module supports retry and split responses from AHB slaves.
15.7.4.1
Retry and split
When the DMAC receives a retry or split response from an AHB slave during DMA transfer, it
negates bus temporarily to reconstruct the contents to be retransmitted.
Figure 15-11 shows an example of receiving a retry response during INCR4 DMA transfer.
HBUSREQ
HGRANT
HCLK
CPU
HMASTER
HTRANS
HADDR
HWRITE
Control
HWDATA
HRDATA
HREADY
HRESP
DMACA[19:16]
BC
DMACA[15:0]
TC
Figure 15-11 Increment/Lap beat transfer (example of INCR4 block transfer)
When DMAC negates bus temporarily, the channel received retry/split responses is continuously
selected by DMAC's priority controller that transfer operation is able to start even though higher
priority channel requests the bus
HDMAC
N S
S
S
N
S
SA
SA SA SA DA DA
INCR4
INCR4
D1
D1
D2 D3
D4
OK
0x0
0x0
CPU
HDMAC
S
S
I
N
I
DA DA
DA
INCR
D2 D3
D4
D4
OK
RETRY
15-33