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MB86R02 'Jade-D' Hardware Manual V1.64
27.6.12
I2SxSTATUS register
Address
Bit
31
30
29
Name
TBERR RBERR FERR
R/W
R
R
R/W R/W R/W R/W R/W R/W
Initial
0
0
0
Bit
15
14
13
Name
(Reserved)
R/W
R
R
R
Initial
0
0
0
Bit field
No.
Name
31
TBERR
In order to set block size of DMA transmission channel to larger value than I2S
transmission FIFO threshold to operate, set this bit to "1" and stop the channel. When
TBERR is "1" and TBERM of INTCNT register is "0", interrupt to CPU occurs.
This becomes "0" by software reset.
30
RBERR
In order to set block size of DMA reception channel to larger value than I2S transmission
FIFO threshold to operate, set this bit to "1" and stop the channel. When RBERR is "1"
and RBERM of INTCNT register is "0", interrupt to CPU occurs.
This becomes "0" by software reset.
29
FERR
Occurrence of frame error is indicated. This bit is set to "1" in the following cases:
•
•
When FERR is "1" and FERRM of INTCNT register is "0", interrupt to CPU occurs. Writing
"1" from CPU clears the value to "0".
This becomes "0" by software reset.
28
TXUDR1
When transmission FIFO underflows at the top of frame, the value is set to "1". Writing "1"
from CPU clears the value to "0".
This becomes "0" by software reset.
27
TXUDR0
When transmission FIFO underflows during frame transmission (from 2nd bit word to the
last frame of the word), the value is set to "1". Writing "1" from CPU clears the value to "0".
This becomes "0" by software reset.
26
TXOVR
When transmission FIFO overflows, the value is set to "1" indicating transmission data is
written in the condition that transmission FIFO is full. The value "1" indicates 1 word or
more of transmission data is deleted.
When TXOVR is "1" and TXOVM of INTCNT register is "0", interrupt to CPU occurs.
Writing "1" from CPU clears the value to "0".
This becomes "0" by software reset.
25
RXUDR
When reception FIFO underflows, the value is set to "1" indicating read access is carried
out to reception FIFO in the condition that reception FIFO is empty.
Writing "1" from CPU clears the value to "0".
This becomes "0" by software reset.
24
RXOVR
When reception FIFO overflows, the value is set to "1" indicating reception is carried out in
the condition that reception FIFO is full. The value "1" indicates 1 word or more of
reception data is deleted.
When RXOVR is "1" and RXOVM of INTCNT register is "0", interrupt to CPU occurs.
Writing "1" from CPU clears the value to "0".
This becomes "0" by software reset.
23-20
(Reserved)
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
ch0：FFEE_0024 (h)
28
27
26
25
TXUDR
TXUDR
TXOVR RXUDR RXOVR
1
0
0
0
0
0
12
11
10
9
TXNUM
R
R
R
R
0
0
0
0
Frame synchronous signal is not able to be received with the set frame rate in the
free-running mode (FRUN = 0 of CNTREG) and the slave mode (MSMD = 0 of
CNTREG)
The next frame synchronous signal is received during frame transmission/reception in
the slave mode (MSMD = 0 of CNTREG), not free-running mode (FRUN = 1 of
CNTREG)
24
23
22
21
(Reserved)
R
R
R
0
0
0
0
8
7
6
5
(Reserved)
R
R
R
R
0
0
0
0
Description
20
19
18
17
EOPI
BSY
TXFI
RXFI
R
R/W
R
R
0
0
0
0
4
3
2
1
RXNUM
R
R
R
R
0
0
0
0
27-19
16
R
0
0
R
0
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