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MB86R02 'Jade-D' Hardware Manual V1.64
16.4.2.
Data Formats
16.4.2.1.
Host Interface (clock timing and phase)
HOST XCS
"H"
HOST SCK
"L"
HOST DI
"L"
HOST DO
"L"
necessary for
(minimum) 2 cycle/HCLK.
16.4.2.2.
Reset Frame
The arrangement of the data byte inputs from the host CPU is a specific one. The byte counter of
the EXTIF unit will malfunction if the HOSTIF module is initialized while the host CPU is
communicating with the HOSTIF module (for example due to an initialization by the MB86R02's
watchdog timer (WDT) or by initialization via a RST-CMD). In this case, the arrangement of the
data bytes would be mistakenly interpreted. It is therefore necessary to use a reset frame when
initializing when the HOSTIF module is communicating.
Reset Frame
HOST SCK
HOST XCS
When the SCLK never reaches the period
when the XCS signal is active
Condition of XCS width
necessary for
(minimum) 2 cycle/HCLK.
Ex.) 25nS/HCLK=83MHz
50nS/HCLK=41MHz
100nS/HCLK=20MHz
16.4.2.3.
Signal input format from the host CPU
The phase relationships of the HOST SCK, HOST XCS, and HOST DI signals is as follows.
16-8
Time when HOSTIF
captures DI.
Figure 16-9 Host Interface (clock timing and phase)
Hold time
necessary for
(minimum) 6 cycle/HCLK.
Ex.) 75nS/HCLK=83MHz
150nS/HCLK=41MHz
300nS/HCLK=20MHz
Figure 16-10 Reset Frame
(Clock Phase and Polarity : CPOL=0 , CPHA=0)
Time when HOSTIF
outputs DO.
The byte counter of
EXTIF is initialized.
"H"
"L"
"L"
"L"
First byte (CMD byte)
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