Interrupt Status Mask Register (Cistm) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

7.4.5 Interrupt status mask register (CISTM)

Address
Bit 31 30 29
INT31M
Name (Reserved)
ASK
R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name (Reserved)
R/W R/W R/W R/W
Initial value 0 0 0
Bit field
Number Name
31 INT31 Mask
30-29 (Reserved)
28 INT28 Mask
27 INT27 Mask
26 INT26 Mask
25 INT25 Mask
24 INT24 Mask
FFF4_2000 + 14h
28 27 26 25
INT28M INT27M INT26M INT25M
ASK ASK ASK ASK
R/W R/W R/W R/W
0 0 0 0
12 11 10 9
R/W R/W R/W R/W
0 0 0 0
Interrupt for MediaLB. INT information becomes valid by writing "1" to this bit.
0 Mask (initial value)
1 INT31 valid
Reserved
Writes are ignored. Reads will return a '0' at all times.
Interrupt for HBUS2AXI. INT information becomes valid by writing "1" to this bit.
0 Mask (initial value)
1 INT28 valid
Interrupt for MBUS2AXI Draw. INT information becomes valid by writing "1" to this bit.
0 Mask (initial value)
1 INT27 valid
Interrupt for MBUS2AXI Display Capture. INT information becomes valid by writing "1" to this
bit.
0 Mask (initial value)
1 INT26 valid
Interrupt for AHB2AXI. INT information becomes valid by writing "1" to this bit.
0 Mask (initial value)
1 INT25 valid
Interrupt for AHB2AXI (AHB Bus). INT information becomes valid by writing "1" to this bit.
0 Mask (initial value)
24 23 22 21
INT24M
(Reserved)
ASK
R/W R/W R/W R/W
0 0 0 0
8 7 6 5
INT5
MASK
R/W R/W R/W R/W
0 0 0 0
Function
20 19 18 17
R/W R/W R/W R/W
0 0 0 0
4 3 2 1
INT3 INT2 INT1
(Res)
MASK MASK MASK
R/W R/W R/W R/W
0 0 0 0
16
R/W
0
0
INT0
MASK
R/W
0
7-9