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MB86R02 'Jade-D' Hardware Manual V1.64
PLL synchronisation losses pll_bad_cnt
COMPHYCFG0
Register address BaseAddress + 100
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19
Field name
COMAPCFG_reserved0
R/W
Reset value
common APIX configuration 0
Bit 31 - 19
COMAPCFG_reserved0
reserved
Bit 18
En_OffsetComp
Enable Offset Compensation (0=power OFF, 1=power ON)
Bit 17
SwRstToPHY
SW reset to PHY, 0=inactive, 1=active
Bit 16
EnRstToPHY
enable reset from Ashells to PHY, 0=disabled, 1=enabled
Bit 11 - 0
RXEyeTime
Measurement period for RxEye, 1lsb = 64ns (16*clk250 counts)
COMPHYCFG1
Register address
BaseAddress + 104
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
Field name
R/W
Reset value
common APIX configuration 1
Bit 31 - 16
MiscCfg
reserved
Bit 11 - 8
Atst_sel
Select use of ATST pad 0: not used 1: Vco control voltge 2: Bandgap voltage 3: Reference current
Bit 4
Mask_pll_good
Masks pllGood for reset in digital 0: pll_good + reset_n signals used to reset digital, 1: only reset_n signal is used to reset digital
Bit 3
Reserved
Do not modify
APPLLCFG
Register
BaseAddress + 10C
address
Bit number
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
Field name
En_PLL
APPLLCFG_reserved0
R/W
RW
Reset value
0
H
PLL/Oscilator configuration
Bit 31
En_PLL
Enable PLL (0=power OFF, 1=power ON)
Bit 30 - 24
APPLLCFG_reserved0
PLL/Oscilator configuration reserved
Bit 23 - 20
crgPmpCtrl
Charge Pump Current Control 0000: 5uA, 0001: 10uA, ..., 1111: 80uA,
Bit 12
PhyPllReset
reset the Pll of the connected PHY: 0=reset not asserted; 1=reset asserted
Bit 10 - 8
LoopResistor
Resistor in PLL loop filter, 0..7: 1K, 2K, 4K, 8K, 12K, 15K, 18K ohm
Bit 7
preDiv2
PLL Pre-divider reference clock by 2, 0: no division, 1: divide by 2
Bit 6 - 0
NDiv
PLL Feedback divider ratio 0,1,2,..127 => Divide by 128,128,2..127
H
18
En_OffsetComp SwRstToPHY EnRstToPHY
RWS
RW
0
0
H
H
H
MiscCfg
RW
0
H
H
crgPmpCtrl
RWS
RW
0
3
H
H
17
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RW
RW
1
0
H
H
Atst_sel
Mask_pll_good
RW
RW
0
H
12
11
10
PhyPllReset
LoopResistor preDiv2
RW
RW
1
3
H
RXEyeTime
RW
100
H
4
3
2 1 0
Reserved
RW
1
0
H
H
9
8
7
6 5 4 3 2 1 0
NDiv
RW
RW
0
14
H
H
H
17-15
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