Timing Signal Module (Tsig) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
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Table 22-4 Bitmapping TTL 6bpc
22.5.2.4

Timing Signal Module (TSIG)

22.5.2.4.1 Block Diagram
The following block diagram shows the functional design of the TSIG module (note the stages).
22-32
G5
G6
G7
B2
B3
B4
B5
B6
B7
0
0
0
0
0
0
G5
G6
G7
B2
B3
B4
B5
B6
B7
0
0
0
0
0
0