Fujitsu MB86R02 Jade-D Hardware Manual page 346

MB86R02 'Jade-D' Hardware Manual V1.64
Bit init Name
ial
cfg_sbup_valid_active_length[1]
7 0
cfg_sbup_valid_active_length[0]
6 1
reserved
5
0
reserved
4 0
reserved
3 0
reserved
2 0
reserved
1 0
reserved
0 0
Table 17-21 TX config_byte_11
config_byte_11
Description
APIX PHY (Soft IP): configure high pulse
width of signal 'sbup_valid' (multiples of
core clk cycle)
11: 4 cycles
10: 3 cycles
01: 2 cycles
00: 1 cycle
do not change
do not change
do not change
do not change
do not change
do not change
17-33