Fujitsu MB86617A Manuals

Manuals and User Guides for Fujitsu MB86617A. We have 1 Fujitsu MB86617A manual available for free PDF download: Specification Sheet

Fujitsu MB86617A Specification Sheet

Fujitsu MB86617A Specification Sheet (139 pages)

IEEE1394 Serial Bus Controller for DTV  
Brand: Fujitsu | Category: Controller | Size: 0.61 MB
Table of contents
Table Of Contents2................................................................................................................................................................
Chapter 1 Overview6................................................................................................................................................................
Chapter 2 Features7................................................................................................................................................................
Chapter 3 Chip Block8................................................................................................................................................................
Block Diagram9................................................................................................................................................................
Normal Operation Mode9................................................................................................................................................................
Synchronous Ransmit Fifo Extended Ode10................................................................................................................................................................
Ransmit Fifo E Xtended M Ode10................................................................................................................................................................
Synchronous Eceive Fifo Extended Ode11................................................................................................................................................................
Eceive Fifo E Xtended M Ode11................................................................................................................................................................
Function Of Each Block12................................................................................................................................................................
Phy Layer Control Circuit12................................................................................................................................................................
Link Layer Control Circuit12................................................................................................................................................................
Tsp Ic Interface12................................................................................................................................................................
Cp Ic Interface12................................................................................................................................................................
Data Bridge12................................................................................................................................................................
Chapter 4 Pin Assignment13................................................................................................................................................................
Pin Assignment14................................................................................................................................................................
Corresponding Table Of Mb86617a Pin15................................................................................................................................................................
Outline Drawing Of Package16................................................................................................................................................................
Chapter 5 Pin Function17................................................................................................................................................................
Ieee1394 Interface18................................................................................................................................................................
Isochronous Interface19................................................................................................................................................................
Mpu Interface21................................................................................................................................................................
Other Pins22................................................................................................................................................................
Power/gnd Pin23................................................................................................................................................................
Chapter 6 Internal Register24................................................................................................................................................................
Chapter 7 Internal Register Function Description30................................................................................................................................................................
M Ode-control Register32................................................................................................................................................................
Flag & Status Register34................................................................................................................................................................
I Nstruction Fetch R Egister36................................................................................................................................................................
R Egister37................................................................................................................................................................
Interrupt-factor Indicate Register/interrupt-mask Setting Register37................................................................................................................................................................
Receive Acknowledge Indicate Register38................................................................................................................................................................
A-buffer Data Port Receive/transmit39................................................................................................................................................................
Tsp Transmit Information Setting Register [a40................................................................................................................................................................
Tsp Transmit Information Setting Register [b42................................................................................................................................................................
Transmit Offset Setting Register [a44................................................................................................................................................................
Transmit Offset Setting Register [b45................................................................................................................................................................
Tsp Receive Information Setting Register46................................................................................................................................................................
R Egister [a]49................................................................................................................................................................
R Egister [b]50................................................................................................................................................................
Tsp Status Register51................................................................................................................................................................
Data Bridge Transmit Information Setting Register 1 [a53................................................................................................................................................................
Data Bridge Transmit Information Setting Register 2 [a54................................................................................................................................................................
Data Bridge Transmit Information Setting Register 3 [b55................................................................................................................................................................
Data Bridge Transmit Information Setting Register 4 [b56................................................................................................................................................................
Data Bridge Receive Information Setting Register57................................................................................................................................................................
Transmit Packet Link/split Setting Register58................................................................................................................................................................
Late Packet Decision Range Setting Register [a60................................................................................................................................................................
Late Packet Decision Range Setting Register [b61................................................................................................................................................................
R Eceive I Sochronous P Acket H Eader I Ndicate R Egister 1 [a]62................................................................................................................................................................
R Eceive I Soc Hronous P Acket H Eader I Ndicate R Egister 2 [a]63................................................................................................................................................................
R Eceive I Sochronous P Acket H Eader I Ndicate R Egister 3 [b]64................................................................................................................................................................
R Eceive I Sochronous P Acket H Eader I Ndicate R Egister 4 [b]65................................................................................................................................................................
Fifo Reset Setting Register66................................................................................................................................................................
Data Bridge Transmit/receive Status Register [a67................................................................................................................................................................
Data Bridge Transmit/receive Status Register [b70................................................................................................................................................................
Isochronous Channel Monitor Register73................................................................................................................................................................
Cycle-timer-monitor Indicate Register74................................................................................................................................................................
Ping Time Monitor Register75................................................................................................................................................................
Phy/link Register/address Setting Register76................................................................................................................................................................
Phy/link R Egister A Ccess P Ort77................................................................................................................................................................
Revision Indicate Register78................................................................................................................................................................
T Ransmit Cgms/tsch I Ndicate R Egister [a]79................................................................................................................................................................
T Ransmit Cgms/tsch I Ndicate R Egister [b]80................................................................................................................................................................
Transmit Cgms/tsch Indicate Status Register81................................................................................................................................................................
Transmit Emi/oe Setting Register83................................................................................................................................................................
Chapter 8 Phy/ink Register Function Description85................................................................................................................................................................
Phy/link R Egister T Able86................................................................................................................................................................
P Hysical Register #00 ( Read )88................................................................................................................................................................
P Hysical Register #01 ( Read / Write )89................................................................................................................................................................
P Hysical Register #02 ( Read )90................................................................................................................................................................
P Hysical Register #03 ( Read )91................................................................................................................................................................
P Hysical Register #04 ( Read / Write )92................................................................................................................................................................
P Hysical Register #05 ( Read / Write )93................................................................................................................................................................
P Hysical Register #07, 08, 09 ( Read )95................................................................................................................................................................
P Hysical Register #0a, 0b, 0c ( Read / Write )96................................................................................................................................................................
P Hysical Register #0d, 0e, 0f ( Read / Write )97................................................................................................................................................................
P Hysical Register #10 ( Read )98................................................................................................................................................................
P Hysical Register #11, 12, 13 ( Read )99................................................................................................................................................................
P Hysical Register #14, 15, 16 ( Read )100................................................................................................................................................................
P Hysical Register #17, 18, 19, 1a, 1b, 1c, 1d, 1e ( Read / Write )101................................................................................................................................................................
L Ink Register #00 ( Read / Write )102................................................................................................................................................................
L Ink Register #01 ( Read / Write )103................................................................................................................................................................
L Ink Register #02 ( Read / Write )104................................................................................................................................................................
L Ink Register #03 ( Read / Write )105................................................................................................................................................................
Chapter 9 Instructio N106................................................................................................................................................................
I Nstruction C Ode T Able107................................................................................................................................................................

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