Function Summary Of The Blocks - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
32 bit general-purpose timer (32 bit timer) × 2ch

APB_TOP_1 (32 bit/41.5 MHz)
This block acts as a bridge between the AHB2 bus via the APBBRG1 async module and the
following low-speed peripheral resources:
I2C controller × 2ch

CAN controller × 2ch

UART (ch2 and ch3) × 2ch

A/D converter (ADC) × 4ch

APB_TOP_2 (32 bit/41.5 MHz)
This block acts as a bridge between the AHB2 bus via the APBBRG2 async module and the
following low-speed peripheral resources:

PWM controller (PWM) x 8ch

SPI controller (SPI) x 2

Chip control module (CCNT)
UART (ch4 and ch5) × 2ch


Function Summary of the Blocks

Function
CPU core
Bus architecture
Interrupts
nterrupt levels are settable by channel
Clock
Reset
Remap
External bus interface Three chip select signals
DDR2 controller
1-6
ARM926EJ-STM processor core
Core operation frequency: 333MHz
16KB instruction cache
16KB data cache
Tightly-Coupled memory for 16KB instruction (ITCM)
Tightly-Coupled memory for 16KB data (DTCM)
ETM9CS Single and JTAG ICE debugging interface
Java acceleration (Jazelle technology)
Multilayer AHB bus architecture
ransfer between main memory and each bus master via 64 bit AXI bus
High-speed interrupt × 1ch (software interrupt)
Normal interrupt × 64ch (external interrupt × 4ch + built-in internal interrupt × 60ch)
PLL multiplication: selectable
Operation frequency: 333MHz (CPU), 83MHz (AHB1/2), 166MHz (AHB3), 41.5MHz (APB)
Low power consumption mode (clock to ARM and module is stoppable)
Hardware reset, software reset, and watchdog reset
ROM area can be mapped to embedded SRAM area
Provided 32M byte address space in each chip select
Supported 16/32 bit width SRAM/Flash ROM connection
Programmable weight controller
Encrypted ROM compound engine
Supported DDR2SDRAM
Connectable capacity: 256 ~ 512M bit × 2 or 256 ~ 512M bit × 1
I/O width: Selectable from ×16/×32 bit
Max. transfer rate (32 bit): 166MHz/333Mbps
Outline