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MB86R02 'Jade-D' Hardware Manual V1.64
Transfer setting
Operation
Abnormality When reading to transmission FIFO
Master mode (MSMD = 1)
Stop
Stop operation has following states:
Transmission stop:
Transmission FIFO becomes empty
without sending data from internal
memory to I2S transmission FIFO.
Reception stop:
Data does not need to be transferred
from I2S reception FIFO to internal
memory.
To maintain start bit to "1"
Keep outputting frame synchronous
signal in the free-running mode. In
the burst mode, do not output the
signal when transmission FIFO
becomes empty.
Transmission stop:
TXENB = 1: Keep outputting empty
frame bit when transmission FIFO
becomes empty.
TXENB = 0: Transmission FIFO
becomes empty and transmission
serial data bus becomes in high
impedance. Do not send the data
in transmission FIFO at writing "0" to
TXENB. Writing to transmission
FIFO stops.
Reception stop:
Write "0" to RXENB, then reception
FIFO becomes empty and frame
reception operation stops.
To make start bit "0"
Write "0" to start bit, then
transmission/reception FIFO
becomes empty.
The clock supply to the internal
serial control part stops regardless
of TXENB and RXENB statuses as
well as I2S_SCKX output to the
external part and frame synchronous
signal output.
occurs with having it empty, output
empty frame bit.
When writing to transmission FIFO
occurs with having it full, set
TXOVR to "1".
If read access to reception FIFO
occurs while it is empty, set RXUDR
of STATUS register to "1".
If writing to reception FIFO occurs
with having it full, set RXOVR of the
register to "1".
Slave mode (MSMD = 0)
To maintain start bit to "1"
Transmission stop:
Keep outputting empty frame bit after
transmission FIFO becomes empty in
order to maintain this bit to TXENB =
1. When the value is changed to "0",
transmission FIFO becomes empty
and transmission serial data bus
becomes in high impedance. Do not
send the data in transmission FIFO at
writing "0" to TXENB. Stop writing to
transmission FIFO.
Reception stop:
Write "0" to RXENB, then reception
FIFO becomes empty and frame
reception operation stops.
To make start bit "0"
Write "0" to start bit, then
transmission/reception FIFO
becomes empty. Stop transmission/
reception regardless of TXENB and
RXENB statuses.
When reading to transmission FIFO
occurs with having it empty, output
empty frame bit.
When writing to transmission FIFO
occurs with having it full, set TXOVR
to "1". When read access occurs to
reception FIFO with having it empty,
set RXUDR of STATUS register to
"1".
When writing to reception FIFO
occurs with having it full, set RXOVR
of the register to "1".
If it is not input with the frame rate
defined frame synchronous signal in
the free-running mode, set FERR bit
of the register to "1".
If the next frame synchronous signal
is input before completing 1 frame
transmission in the burst mode, set
FERR bit of the register to "1".
27-27
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