Composite Synchronous Signal - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

18.8.2 Composite synchronous signal

When the EEQ bit of the DCM register is "0", the CSYNC signal output waveform is as shown

Fig 11.12 Composite Synchronous Signal without Equalizing Pulse

When the EEQ bit of the DCM register is "1", the equalizing pulse is inserted into the CSYNC signal,

producing the waveform shown below.

Fig 11.13 Composite Synchronous Signal with Equalizing Pulse

The equalizing pulse is inserted when the vertical blanking time period starts. It is also inserted

three times after the vertical synchronization time period has elapsed.