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MB86R02 'Jade-D' Hardware Manual V1.64
L3TC (L3 layer Transparency Control)
Register
DisplayBaseAddress + 0xC0
address
Bit number
15
Bit field name
L3ZT
R/W
RW
Initial value
0
This register sets the transparent color for the L3 layer. When L3TC = 0 and L3ZT = 0, color 0 is
displayed in black (transparent).
This register corresponds to the MLTC register for previous products.
Bit 14 to 0
L3TC (L3 layer Transparent Color)
Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 15
L3ZT (L3 layer Zero Transparency)
Sets handling of color code 0 in L3 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
L0ETC (L0 layer Extend Transparency Control)
Register
DisplayBaseAddress + 0x1A0
address
Bit number
31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
L0ETZ
R/W
RW
Initial value
0
This register sets the transparent color for the L0 layer. The 24 bits/pixel transparent color is set
using this register. The lower 15 bits of this register are physically the same as L0TC. Also, L0ETZ
is physically the same as L0TZ.
When L0ETC = 0 and L0EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0
L0ETC (L0 layer Extend Transparent Color)
Sets transparent color code for the L0 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 31
L0EZT (L0 layer Extend Zero Transparency)
Sets handling of color code 0 in L0 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
18-110
14
13
12
11
10
Reserved
R0
0
9
8
7
6
5
L3TC
RW
Don't care
L0TEC
RW
4
3
2
1
0
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