Interrupt Registers; Interrupt Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
18.11.18

Interrupt registers

18.11.18.1

Interrupt register list

BaseAddress = HostBaseAddress (=0xF1FC_0000)
Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
FIFC
0020
FIFC
0024
IST (Interrupt STatus)
Register
HostBaseAddress + 20
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
*1 Reserved
This register indicates the current interrupt status. It shows that an interrupt request is issued when
"1" is set to this register. The interrupt status is cleared by writing "0" to this register.
Bit 0 CERR (Command Error Flag)
Indicates drawing command execution error interrupt
Bit 1 CEND (Command END)
Indicates drawing command end interrupt
Bit 2 VSYNC0 (Vertical Sync. of display 0)
Indicates vertical interrupt synchronization
Bit 3 FSYNC0 (Frame Sync. of display 0)
Indicates frame synchronization interrupt
Bit 4 SYNCERR0 (Sync. Error of display 0)
Indicates external synchronization error interrupt
Bit 5 REGUD0 (Register update of display 0)
Indicates register update interrupt
Bit 6 VSYNC1 (Vertical Sync. of display 1)
Indicates vertical interrupt synchronization
Bit 7 FSYNC1 (Frame Sync. of display 1)
Indicates frame synchronization interrupt
Bit 8 SYNCERR1 (Sync. Error of display 1)
Indicates external synchronization error interrupt
Bit 9 REGUD1 (Register update of display 1)
Indicates register update interrupt
H
Reserved Resv
R0
R0W0
0
IST
IMASK
Reserved
R0
0 0
8 7 6 5 4 3 2 1
IST
IMASK
IST
RW0
0
18-249
0