Pwmx Duty Register (Pwmxdr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
25.7.5

PWMx duty register (PWMxDR)

This register is to set duty cycle of the pulse.
Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0
Bit field
No. Name
31-1 (Reserved)
6
15-0 DR
APBCLK
BASECLK
PWM
25-8
ch0：FFF4_1000 + 0C
ch1：FFF4_1100 + 0C
ch2：FFF4_6000 + 0C
ch3：FFF4_6100 + 0C
ch4：FFF4_7000 + 0C
ch5：FFF4_7100 + 0C
ch6：FFF4_8000 + 0C
ch7：FFF4_8100 + 0C
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
0 0 0 0
Reserved bits.
Write access is ignored. The read value of these bits is always "0".
Duty cycle shown in Figure 14-4 is set.
DR[15:0]
0 0 BASECLK
1 1 BASECLK
| |
65535 65535 BASECLK
Phase
Figure 25-4 Setting parameter
H
H
H
H
H
H
H
H
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
DR[15:0]
0 0 0 0
Description
Duty cycle
(Setting prohibited)
Duty
Pulse width (1 cycle)
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
0 0 0 0
Next cycle (skippable)
16
R
0
0
0