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MB86R02 'Jade-D' Hardware Manual V1.64
6.3
Software Interface .............................................................................................................. 6-3
6.3.1
Format of Register Description ....................................................................................... 6-3
6.3.2
Global Address ............................................................................................................... 6-4
6.3.3
Register Summary .......................................................................................................... 6-4
Register Description .......................................................................................................................... 6-4
6.4
Processing Mode ................................................................................................................ 6-8
6.4.1
Parameter setting for 666MHz PLL clock ....................................................................... 6-8
6.4.1.1
Parameter setting for SSCG-speed of 15KHz ......................................................... 6-8
6.4.1.2
Parameter setting for SSCG-speed of 20KHz ......................................................... 6-9
6.4.1.3
Parameter setting for SSCG-speed of 35KHz ....................................................... 6-10
6.4.1.4
Parameter setting for SSCG-speed of 50KHz ....................................................... 6-10
6.5
Control Flow ..................................................................................................................... 6-11
6.5.1
Operation ...................................................................................................................... 6-11
7
CCNT (Chip Control) ..................................................................................................................... 7-1
7.1
Overview ............................................................................................................................. 7-1
7.2
Features ............................................................................................................................. 7-2
7.3
Supply clock ....................................................................................................................... 7-2
7.4
Registers ............................................................................................................................ 7-3
7.4.1
Register list ..................................................................................................................... 7-3
7.4.2
CHIP ID register (CCID) ................................................................................................. 7-5
7.4.3
Soft reset register (CSRST) ............................................................................................ 7-6
7.4.4
Interrupt status register (CIST) ....................................................................................... 7-7
7.4.5
Interrupt status mask register (CISTM) .......................................................................... 7-9
7.4.6
GPIO interrupt status register (CGPIO_IST) ................................................................ 7-11
7.4.7
GPIO interrupt status mask register (CGPIO_ISTM).................................................... 7-11
7.4.8
GPIO interrupt polarity setting register (CGPIO_IP) ..................................................... 7-13
7.4.9
GPIO interrupt mode setting register (CGPIO_IM) ....................................................... 7-13
7.4.10
AXI bus wait cycle set register (CAXI_BW) .................................................................. 7-15
7.4.11
AXI priority setting register (CAXI_PS) ......................................................................... 7-17
7.4.12
Multiplex mode setting register (CMUX_MD) ............................................................... 7-19
7.4.13
External pin status register (CEX_PIN_ST) .................................................................. 7-21
7.4.14
MediaLB set register (CMLB) ....................................................................................... 7-22
7.4.15
MBUS2AXU set register (CMBUS) ............................................................................... 7-24
7.4.16
Mode switch register like endian etc. (CBSC) .............................................................. 7-25
7.4.17
DDR2 Interface reset control register (CDCRC) ........................................................... 7-27
7.4.18
Soft reset register 0 for macro (CMSR0) ...................................................................... 7-28
7.4.19
Soft reset register 1 for macro (CMSR1) ...................................................................... 7-30
7.4.20
Soft reset register 2 for macro (CMSR2) ...................................................................... 7-33
8
Remap Boot Controller (RBC) ....................................................................................................... 8-1
8.1
Outline ................................................................................................................................ 8-1
8.2
Features ............................................................................................................................. 8-1
8.3
Block Diagram .................................................................................................................... 8-1
8.4
Supply clock ....................................................................................................................... 8-2
8.5
Register .............................................................................................................................. 8-2
8.5.1
Register list ..................................................................................................................... 8-2
8.5.2
Remap control register (RBREMAP) .............................................................................. 8-4
8.5.3
VINITHI control register A (RBVIHA) .............................................................................. 8-5
8.5.4
INITRAM control register A (RBITRA) ............................................................................ 8-6
8.6
Operation ............................................................................................................................ 8-7
8.6.1
RBC reset ....................................................................................................................... 8-7
8.6.2
Remap control................................................................................................................. 8-7
8.6.3
VINITHI control ............................................................................................................... 8-7
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