Operation; Transfer Modes; Block Transfer - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

15.7 Operation

This section describes the operation of the DMAC.

The DMAC has 3 transfer modes which are set using DMACB.MS[1:0].

In block transfer mode, DMA transfer is specified by the number of blocks (DMACA/BC) to be

executed by 1 transfer request. When the number of transfer (DMACA/TC) is set to a value other

than "0", TC is decremented by 1 after completing the DMA transfer of BC. After the last transfer

(BC is 4'h0 and TC is 16'h0000), DMA transfer is completed.

Transfer gap

After completing BC transfer, DMAC temporarily negates the bus request to the arbiter in block

transfer mode. This operation prevents the DMAC from blocking the bus.

This transfer gap can be used to update the register settings (e.g. disable/interruption setting) to

the DMAC during DMA transfer.

Transfer request

Three types of request are valid in this mode: request by software, external request (DREQ) and

peripheral request (IDREQ)..

• Software request

Set "1" to DMACA/ST and set 5'b00000 to DMACA/IS

• External request

Set "0" to DMACA/ST, and set 5'b01110 (rising edge of transfer request) or 5'b01111 (falling

edge of transfer request) to DMACA/IS

• Peripheral request

Set "0" to DMACA/ST, and set 5'b1**** (rising edge of transfer request) to DMACA/IS

When a external request or peripheral request is selected, the DMAC detects the transfer

request edge. When BC's DMA transfer is executed by either of those requests, the DMAC is

unable to detect the next transfer; however it is able to detect the next transfer request after BC's

DMA transfer has been completed.