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MB86R02 'Jade-D' Hardware Manual V1.64
If using a mixed setting of SSCG_FSTEP and SSCG_FOFFSET (both values are not zero) the SSCG
will generate an interrupt in the first 32 SSCG_periods. These interrupts can be ignored. An illegal
configuration setting will periodically generate an interrupt in SSCG_period cycles.
Figure 6-2 SSCG setting sequence of the frequency offset and SSCG mode
Note:
When SSCG_PEAK_FREQUENCY is set to 1, the modulation peak value will be doubled. In order to
maintain the same modulation peak, the values of SSCG_FSTEP and SSCG_FOFFSET must therefore be
divided by 2.
Note:
Please note that an important Application Note exists concerning EMI optimization and the SSCG.
You should refer to this document before implementing SSCG usage, as it contains essential information
about current restrictions in the hardware.
Link:
http://www.fujitsu.com/emea/services/microelectronics/gdc/gdcdevices/mb86r02-jade-d.html
6-2
Foffset and Fstep
Setting of
Sscg_foffset
Sscg_fstep
Sscg_peak_frequency =1
Disable interrupt
Sscg_en = 1
Wait for 32xsscg_period
Reset interrupt
Enable interrupt
SSCG runs
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