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MB86R02 'Jade-D' Hardware Manual V1.64
Bit 4: MSS (Master Slave Select)
This is the master/slave selection bit.
At writing
MSS
0
Stop condition is generated and state becomes slave mode after the transfer
1
State becomes master mode and start condition is generated to start transfer
This bit is cleared when 'arbitration lost' occurs during master transmission and the state becomes
slave mode.
Restrictions:
In a multimaster environment, please prohibit other masters from transmitting general
call addresses simultaneously with this module, as well as using 'arbitration lost' for this
module at the second byte or later.
Bit 3: ACK (ACKnowledge)
This is the acknowledge permission bit at receiving data.
On reads/writes
ACK
0
Acknowledge has not occurred.
1
Acknowledge has occurred.
This bit is disabled on address data reception in slave mode.
Bit 2: GCAA (General Call Address Acknowledge)
This is the acknowledge permission bit on receiving general call address.
At reading/writing
GCAA
0
Acknowledge has not occurred.
1
Acknowledge has occurred.
Bit 1: INTE (INTerrupt Enable)
This is the interrupt permission bit.
At reading/writing
INTE
0
Interrupt is prohibited
1
Interrupt is enabled
When this bit is "1" and INT bit is "1" an interrupt occurs.
29-10
State
State
State
State
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