Fujitsu MB86R02 Jade-D Hardware Manual page 391

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MB86R02 'Jade-D' Hardware Manual V1.64

module XC9572XL (DCKi, HSi,VSi,Di, DCK0,HS0,VS0,D0, DCK1,HS1,VS1,D1);

input DCKi,HSi,VSi;

input[18:0] Di;

output DCK0,HS0,VS0, DCK1,HS1,VS1;

output[18:0] D0,D1;

reg HS0,HS1, VS0,VS1, DCK0,DCK1;

reg[18:0] D0,D1;

always @(posedge DCKi) begin

HS0 <= HSi; HS1 <= HS0;

VS0 <= VSi; VS1 <= VS0;

DCK0 <= (HS0&!HSi)? 0: !DCK0; // sync to ref edge : flip

DCK1 <= DCK0;

if(DCK0) D0 <= Di;

if(DCK1) D1 <= Di;