Fujitsu MB86R02 Jade-D Hardware Manual page 89

MB86R02 'Jade-D' Hardware Manual V1.64
CCLK
PADM[2:0]
HBDM[2:0]
HADM[2:0]
Figure 5-6 Clock structure: non-modulated clocks, part 1
STOP | PAGATE[X]
DIV
Gate
1/L
X
STOP
Gate
STOP | HBGATE[X]
DIV
Gate
1/L
X
STOP | HAGATE[X]
DIV
Gate
1/L
X
PACLKX_O
(IRC,....UART)
PACLKcrg_O
(CRG)
HBCLKMLB_O
(MLB)
HACLKY_O
(MLB, I2S, SD)
5-9