Line Control Register (Urtxlcr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6.7 Line control register (URTxLCR)

ch0：FFFE_1000 + 0Ch ch1：FFFE_2000 + 0Ch ch2：FFF5_0000 + 0Ch
Address
ch3：FFF5_1000 + 0Ch ch4：FFF4_3000 + 0Ch ch5：FFF4_4000 + 0Ch
Bit 31 30 29
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value X X X
Bit 15 14 13
Name
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
valu X X X
e
Bit No. Bit name
31:8 Unused
7 DLAB
6 SB
5 SP
4 EPS
3 PEN
2 STB
1:0 WLS1:0
* Bit7:0 = 00h, after reset
28-10
28 27 26 25
X X X X
12 11 10 9
(Reserved)
X X X X
Reserved bit (input "0" at writing)
Divisor Latch Access Bit (divider latch access bit)
0: Disable
Reception FIFO register reads with address 0
Transmission FIFO register writes with address 0
IER register reads and writes with address 1
1: Enable
DLL register reads and writes with address 0
DLM register reads and writes with address 1
TST register writes with address 7
Set Break (break transmission)
1: The SOUT signal forcibly becomes "0"
Stick Parity (fixed parity)
0: Parity bit is determined by EPS and PEN
1: Parity bit is fixed as follows depending on the status of EPS and PEN (checked at
transmission, generation, and reception)
Parity is "1" at PEN = 1 and EPS = 0
Parity is "0" at PEN = 1 and EPS = 1
Even Parity Select (parity selection)
0: Odd parity
1: Even parity
Parity Enable (parity enable)
0: Parity is not sent nor checked
1: Parity is sent and checked
Parity bit is added to end of data area, and stop bit comes last
Number of Stop Bit (stop bit length)
0: 1 bit
1: 1.5 bit (data length: 5)
2 bit (data length: 6 ~ 8)
Word Length Select (transmission/reception data length)
00: 5 bit
01: 6 bit
10: 7 bit
11: 8 bit
24 23 22 21
(Reserved)
X X X X
8 7 6 5
DLAB SB SP EPS
X 0 0 0
Function
20 19 18 17
X X X X
4 3 2 1
PEN STB WLS1 WLS0
0 0 0 0
16
X
0
0