Line Status Register (Urtxlsr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6.9 Line status register (URTxLSR)

ch0：FFFE_1000 + 14h ch1：FFFE_2000 + 14h ch2：FFF5_0000 + 14h
Address
ch3：FFF5_1000 + 14h ch4：FFF4_3000 + 14h ch5：FFF4_4000 + 14h
Bit 31 30 29
Name
R/W R R R
Initial value X X X
Bit 15 14 13
Name
R/W R R R
Initial
valu X X X
e
Bit No. Bit name
31:8 Unused
7 ERRF
6 TEMT
5 THRE
4 BI
3 FE
2 PE
1 OE
0 DR
* Bit7:0 = 60h, after reset
28-12
28 27 26 25
R R R R
X X X X
12 11 10 9
(Reserved)
R R R R
X X X X
Reserved bit
Error in RCVR FIFO (error in reception FIFO)
This bit is set even 1 error of parity, flaming, or break detection is in reception
FIFO.
If data including error (except the one set ERRF flag) is not in reception FIFO at
reading LSR register, this is reset.
Transmitter Empty (transmission shift register empty)
When both Transmission shift register and Transmission FIFO register become
empty, TEMT is set to "1".
Transmitter FIFO Register Empty (transmission register empty)
When Transmission FIFO register is empty and ready to accept new data, THRE
is set to "1".
This bit is cleared at sending data to Transmission shift register.
Break Interrupt (break reception)
This bit is set when SIN is held in "0" more than transmission time (start bit + data
bit + parity + stop bit.) BI is reset by CPU reading this register.
Framing Error (flaming error)
This bit is set when reception data does not have valid stop bit. FE is reset by
CPU reading this register.
Parity Error (parity error)
This bit is set when reception data does not have valid parity bit.
PE is reset by CPU reading this register.
Overrun Error (overrunning error)
This bit is set when reception FIFO is full and receives the next reception data.
OE is reset by CPU reading this register.
Data Ready (reception data existed)
This bit shows 1 byte or more of data is in FIFO.
This bit is set when data is in FIFO and reset after reading all data in FIFO.
24 23 22 21
(Reserved)
R R R R
X X X X
8 7 6 5
ERRF TEMT THRE
R R R R
X 0 1 1
Function
20 19 18 17
R R R R
X X X X
4 3 2 1
BI FE PE OE
R R R R
0 0 0 0
16
R
X
0
DR
R
0