Output Signal Control; Output Circuit Example - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
The SC0en (screen"0" enable) field of the MDC register defines which layers and cursors are included
in screen "0".
The SC1en (screeen"1" enable) field of the MDC register defines which layers and cursors are
included in screen "1".
bit-0 ---- L0 is included
bit-1 ---- L1 is included
:
bit-5 ---- L5 is included
bit-6 ---- Cursor0 is included
bit-7 ---- Cursor1 is included
18.6.10.3

Output Signal Control

Two screen data streams are output in multiplex mode as follows:
DCLKOn
ref edge
HSYNCn
DRn,DGn,DBn
DEn
18.6.10.4

Output Circuit Example

A single CPLD can demultiplex the RGB 6bit/component video data stream (Xilinx device shown here):
MB86R02
DCLKOn
HSYNCn
VSYNCn
DEn
DRn[7:2]
DGn[7:2]
DBn[7:2]
(POM=0,DCKed=0)
18-32
even clocks
XC9572XL-TQ100
(SE mode)
DCKi
HSi
VSi
Di[18]
Di[17:0]
sc0 is first
sc0 sc1
DCK0 DCLK0
HS0 HSYNC0
VS0 VSYNC0
D0[18] DE0
D0[17:0]
R0,G0,B0
DCK1 DCLK1
HS1 HSYNC1
VS1 VSYNC1
D1[18] DE1
D1[17:0]
R1,G1,B1
display
device "0"
display
device "1"