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MB86R02 'Jade-D' Hardware Manual V1.64
(2) PLL oscillation frequency is changed by PLL mode ("M" and "m" of LUWMODE in
the 5.1.2 PLL control register (CRPR)
XRST
PLL reset
CLK
1/M PLL clock
CCLK
PLLREADY
PLLBYPASS
PLLMODE[4:0]
Figure 5-9 PLL oscillation stabilization waiting state after PLL mode change
(3) Returning from stop mode after external interrupt
(4) Watchdog reset is asserted
Frequency change
Table 5-3 Setting example of input frequency and multiple number
Initial Setting: {PLLBYPASS,
Operation
CRIPM[3:0]}
Freq.
At operation: PLLMODE[4:0]
0
0
0
333M
0
0
0
1
For selection of oscillator frequency, fulfill note in section 5.3
5-12
a)
b)
a)
Clock source change (write PLLBYPASS bit)
b)
Set Disp/Cap/DPERI unit into reset (see register VCCC)
c)
Set the PLL oscillation mode (write PLLMODE bits)
d)
PLL reset de-asserted
e)
PLL ready (PLLREADY can be monitored by PLLRDY bit)
f)
Clock source change (write PLLBYPASS bit)
g)
Deactivate reset at DISP/Cap/DPERI Unit
The oscillation frequency and frequency dividing ratio (M) of PLL (f
PLLMODE[4:0] bit of the PLL control register (CRPR) and the frequency can be
changed during operation (see Table 5-3.)
Do not change PLLMODE[4:0] when the PLLBYPASS bit of the PLL control register
(CRPR) is 0.
The initial value at start up is determined by the external pin PLLBYPASS and
CRIPM[3:0]. To specify PLLSTOP for the initial value, fix the external pin
PLLBYPASS to "1" too.
Ndiv
Pdiv
0
0
64
3
0
1
80
3
PLL oscillation
2
(m
+ 2) CLK
stabilization waiting
cycles
c)
Display/
Oscillator
Reference
1
Clock
Clock
31.25
666.67
333.33
25.00
666.67
333.33
d)
e)
× N) are set by
CLK
333.33
166.67
83.33
333.33
166.67
83.33
166.67
41.67
166.67
41.67
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