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MB86R02 'Jade-D' Hardware Manual V1.64
Bit
init
Name
ial
cfg_sbdown_clk
7
0
cfg_sbdown_daclk_clength[6]
6
0
cfg_sbdown_daclk_clength[5]
5
1
cfg_sbdown_daclk_clength[4]
4
0
cfg_sbdown_daclk_clength[3]
3
0
cfg_sbdown_daclk_clength[2]
2
1
cfg_sbdown_daclk_clength[1]
1
1
cfg_sbdown_daclk_clength[0]
0
0
Table 17-22 TX config_byte_shell1
17-34
config_byte_shell1
Description
AShell: functional meaning of
'sbdown_trigger' when 'cfg_trigger_offset'
is set to 0
0: request
1: strobe (only use with internal APIX PHY)
AShell
configures data rate of downstream
sideband (see tables below)
Note: valid if cfg_sbup_daclk[1:0]
= "10"
AShell: configures cycle time of
sbdown clock (multiples of Ashell
core clock) when sbdown_data are
asynchronous (sbdown_data[1] is
used as sbdown clock) or
cfg_mode_sb is enabled (mode1)
11:recommended minimum (no low
bandwidth mode, AShell and APIX
PHY operate at same core clock
frequency)
20:recommended minimum (low
bandwidth mode 2, AShell and APIX
PHY operate at 62.5 MHz)
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