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MB86R02 'Jade-D' Hardware Manual V1.64
34.5.2
DDR2SDRAM Interface
This is able to connect with DDR2 SDRAM which is in conformance with DDR2-400 in the JEDEC
(JESD79-2C.) The timing rules are described below and the output load condition is according to
the PCB design guideline.
Table 34-18 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS
Item
CMD/ADD setup valid-data from
CK↑
CMD/ADD hold valid-data from CK↑ tVD_hold_CMD
Skew between DQS↑ vs. CK↑
*1: Spec for tck = 6ns (333Mbps) is indicated
Table 34-19 Write Spec (3): DQ-DQS
Item
DQ/DM setup valid-data from DQS
DQ/DM hold valid-data from DQS
*1: Spec for tck = 6ns (333Mbps) is indicated
Table 34-20 Read Spec (1): DQ-DQS
Item
tSETUP DQ from DQS
tHOLD DQ from DQS
*1: Spec for tck = 6ns (333Mbps) is indicated
Table 34-21 Read Spec (2): DQ-R.T.T (RoundTrip Time)
Item
DQS RoundTripTime @CL = 3
(CK_out DRAM DQS_in)
*1: Spec for tck = 6ns (333Mpbs) is indicated
*2: Spec shows total delay value including tDQSCK delay of DRAM
34-20
Symbol
Spec formula
tVD_setup_CMD (tCK/2) - 828
(tCK/2) - 545
Not tCK
tSkew_DQS_CK
dependent
Symbol
Spec formula
tVD_setup_DQ （tCK/4) - 884
（tCK/4) - 776
tVD_hold_DQ
Symbol
Spec formula
- (0.1875*tCK –
tSETUP_DQ
208 )
tHOLD_DQ
0.1875*tCK + 503
Symbol
Spec formula
<Max.> 1112
tRTT_DQS
<Min.> -595
Criteria value (*1)
Min.
Typ.
Max.
2172
–
–
2455
–
–
-1083
–
772
Criteria value (*1)
Min.
Typ.
Max.
616
–
–
724
–
–
Criteria value (*1)
Min.
Typ.
Max.
-917
–
–
1628
–
–
Criteria value (*1)
Min.
Typ.
Max.
-355
–
+1426
Unit
ps
ps
Ps
Unit
ps
ps
Unit
ps
Ps
Unit
ps
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