Fujitsu MB86R02 Jade-D Hardware Manual page 785

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MB86R02 'Jade-D' Hardware Manual V1.64

Operation example of PE flag of bit 2 in the Line status register (LSR) is shown in Figure 28-9.

M ar k st at e

( PE-FI FO )

r egi st er readi ng

Figure 28-9 Operation example of PE flag (setting even parity)

Parity bit is set to "1" or "0" depending on the number of "1" level bit in the 1 data bit. When it is

set to even parity with EPS in the Line control register, the bit is set to "1" or "0" to have total data

bit and "1" level parity bit even number. Likewise, when parity bit is set to odd parity, total

number of "1" level is set to be odd number.

On reception side, the number of "1" level bit of 1 data including input parity bit is counted, and

polarity of the parity set with EPS bit in the Line control register is compared.

For their discrepancy, PE flag of the register becomes "1" by the judgment that problem occurred

in transmitting data. Then the flag becomes "0" by reading the Line status register. This error is

applied to each data in FIFO, and is able to be confirmed when CPU reads first data of FIFO.

1 char act er

N or m al com pl et i on

Abnor m al com pl et i on

Par i t y bi t