Fujitsu MB86R02 Jade-D Hardware Manual page 270

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
Description
No. Name
27- DH[3:0] All channels of DMA stop are controlled.
24 (DMA Halt) When the value other than 4'b0000 is set to this bit, all DMA channels stop and DMA is not
transferred until 4'b0000 is set.
If the value other than 4'b0000 is set during DMA transfer, it is stopped at transfer gap.
Refer to DE bit description for the transfer gap.
These bits are used to stop DMA transfer without resetting each configuration register of all
channels.
0000 Stop release
Other than 0000 Stop of channels
23-0 (Reserved) Reserved bits.
Write access is ignored. Read value of this bit is always "0".
15-7