Supply Clock; Registers; Register List - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

13.5 Supply Clock

AHB clock is supplied to DDR2 controller. Refer to "5. Clock reset generator (CRG)" for
frequency setting and control specification of the clock.

13.6 Registers

This section describes DDR2 controller (DDR2C) register.

13.6.1 Register List

Table 13-2 shows DDR2C register list.
Table 13-2 DDR2C register list
Address
Base Offset
F300_0000 + 00 DRAM Initialization Control Register
H
H
+ 02 DRAM Initialization Command Register [1] DRIC1
H
+ 04 DRAM Initialization Command Register [2] DRIC2
H
+ 06 DRAM CTRL ADD Register
H
+ 08 DRAM Control Mode Register
H
+ 0A DRAM CTRL SET TIME1 Register
H
+ 0C DRAM CTRL SET TIME2 Register
H
+ 0E DRAM CTRL REFRESH Register
H
+ 10 - (Reserved)
H
+ 1F
H
+ 20 DRAM CTRL FIFO Register
H
+ 22 - (Reserved)
H
+ 2F
H
+ 30 AXI Setting
H
+ 32 - (Reserved)
H
+ 4F
H
+ 50 DRAM IF MACRO SETTING DLL Register DRIMSD
H
+ 52 - (Reserved)
H
+ 5F
H
+ 60 DRAM ODT SETTING Register
H
+ 62 - (Reserved)
H
+ 63
H
+ 64 IO buffer setting ODT1
H
+ 66 IO buffer setting OCD
H
+ 68 IO buffer setting OCD2
H
+ 6A - (Reserved)
H
+ 6F
H
+ 70 ODT Auto Bias Adjust
H
+ 72 - (Reserved)
H
+ 83
H
+ 84 ODT Bias Select Register
H
+ 86 - (Reserved)
H
+ 8F
H
+ 90 IO Monitor Register1
H
+ 92 IO Monitor Register2
H
+ 94 IO Monitor Register3
H
+ 96 IO Monitor Register4
H
+ 98 OCD Impedance Setting Register1
H
+ 9A OCD Impedance Setting Register2
H
Register name
Abbreviatio
n
DRIC Initialization control register
Initialization control command register
1
Initialization control command register
2
DRCA Address control register
DRCM Mode control register
DRCST1 Timing setting register 1
DRCST2 Timing setting register 2
DRCR Refresh control register
- Access prohibited
DRCF FIFO control register
- Access prohibited
DRASR AXI operation setting register
- Access prohibited
DDRIFmacro setting register
- Access prohibited
DROS ODT setting register
- Access prohibited
DRIBSODT1 IO ODT1 setting register
DRIBSOCD IO OCD setting register
DRIBSOCD2 IO OCD2 setting register
- Access prohibited
DROABA ODT bias self adjustment register
- Access prohibited
DROBS ODT bias selection register
- Access prohibited
DRIMR1 IO monitor register 1
DRIMR2 IO monitor register 2
DRIMR3 IO monitor register 3
DRIMR4 IO monitor register 4
DROISR1 OCD impedance setting register 1
DROISR2 OCD impedance setting register 2
Description
13-3