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MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No.
Name
23-20
BT[3:0]
These bits are used to select beat transfer on AHB.
(Beat Type)
When these bits are set to Normal or Single, single source access and single destination
access are alternately performed.
If these bits are set to INCR* or WRAP*, contiguous source access and contiguous
destination access are alternately performed.
DMAC has 64 byte of FIFO that is shared in all channels. FIFO is used for INCR* and
WRAP* DMA transfer. Refer to the AMBA specifications (v2.0) for INCR* and WRAP*.
When INCR (undefined length burst) is set, the burst length is specified by the BC bit.
While DMACB/MS are set to block transfer and burst transfer, fixed length burst (INCR*,
WRAP*) and undefined length burst (INCR) are valid.
When DMACB/MS are set to demand transfer, BT should be set to Normal or Single.
19-16
BC[3:0]
These bits are used to specify number of block for block/burst transfer. When transfer
(Block Count)
mode is demand transfer, be sure to set 4'b0000 to BC. Max. block quantity is 16.
These bits are valid when beat transfer type is Normal, Single, or INCR. When other
types of beat (fixed length burst and lap) are set, these bits are ignored. In addition,
they are able to be read during DMA transfer. After single source access and single
destination access are properly completed, normally BC bit is decremented for 1.
[Note]
These bits are settable even beat type bit (BT[3:0]) is INCR, however read data of BC
after starting DMA transfer is always 4'h0 in INCR DMA transfer so that BC does not
need to be monitored during the transfer.
After DMA transfer is completed properly, DMAC sets 4'b0000 to these bits.
15-0
TC[15:0]
These bits are used to specify number of block/burst/demand transfer. Max. number of
(Transfer
transfer is 65536. Any kind of bit type is valid for BT.
Count)
These bits are readable during DMA transfer. After BC becomes "0" and DMA transfer
is properly completed, normally TC bit is decremented for 1 in the Normal or Single mode
(BT = Normal or Single.) In other beat transfer modes (INCR, INCR*, and WRAP*), TC
bit is decremented for 1 after completing consecutive source/destination access
operation (for example, when 4 consecutive source accesses and 4 consecutive
destination accesses are completed, INCR4's TC bit is decremented for 1.)
After DMA transfer is completed properly, DMAC sets 16'h0000 to these bits.
15-10
BT[3:0]
0(h)
Normal (same as Single)
(Initial value)
1(h)-7(h)
Invalid
8(h)
Single (same as Normal)
9(h)
INCR
A(h)
WRAP4
B(h)
INCR4
C(h)
WRAP8
D(h)
INCR8
E(h)
WRAP16
F(h)
INCR16
BC[3:0]
x(h)
Number of blocks minus 1 (initial value: 4'b0000)
TC[3:0]
x(h)
Number of transfers minus 1 (initial value: 16'h0000)
Description
Function
Function
Function
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