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MB86R02 'Jade-D' Hardware Manual V1.64
27.6.13
I2SxDMAACT register
Address
Bit
31
30
29
Name
R/W
R
R
R
Initial
0
0
0
Bit
15
14
13
Name
R/W
R
R
R
Initial
0
0
0
Bit field
No.
Name
31-17
(Reserved)
16
TDMACT
15-1
(Reserved)
0
RDMACT
ch0：FFEE_0028 (h)
28
27
26
25
(Reserved)
R
R
R
R
0
0
0
0
12
11
10
9
(Reserved)
R
R
R
R
0
0
0
0
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
Transmission channel of DMAC (DMA controller) is activated.
After transfer channel starts, software should write "1" to TDMACT to teach I2S that the
transfer channel is active. When TDMACT is "0", transfer request of transmission
channel block is not sent to DMAC.
I2S automatically clears TDMACT every time DMA packet transmission completes.
Writing "0" from CPU clears the value to "0".
This becomes "0" by software reset.
0 Transmission channel of DMAC is stop that TXDREQ is unable to be
detected
1 Transmission channel of DMAC is activated that TXDREQ is able to be
detected
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
The reception channel of DMAC (DMA controller) is activated.
After reception channel starts, software should write "1" to RDMACT to teach I2S that
the channel is active. When RDMACT is "0", transfer request of reception channel
block is not sent to DMAC.
I2S automatically clears RDMACT every time DMA packet reception completes.
Writing "1" from CPU clears the value to "0".
This becomes "0" by software reset.
0 Reception channel of DMAC is stop that RXDREQ is unable to be detected
1 Reception channel of DMAC is active that RXDREQ is able to be detected
24
23
22
21
20
R
R
R
R
R
0
0
0
0
0
8
7
6
5
4
R
R
R
R
R
0
0
0
0
0
Description
19
18
17
16
TDMACT
R
R
R
R/W
0
0
0
0
3
2
1
0
RDMACT
R
R
R
R/W
0
0
0
0
27-21
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