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MB86R02 'Jade-D' Hardware Manual V1.64
13.6.21
IO monitor register 3 (DRIMR3)
This is input level monitor of IO buffer which is used for impedance adjustment of OCD.
Address
Bit
15
14
13
Name
R/W
Initial value
X
X
X
Bit field
No.
Name
15-0
(Reserved)
When input value of IO is read, IO driver should be in the OCD adjustment mode.
The following settings are required:
• Bit 0 of IO buffer setting OCD2 register (68
• Bit 1 of IO buffer setting OCD2 register (68
Remark:
Monitor value is valid only at OCD adjustment.
13.6.22
IO monitor register 4 (DRIMR4)
This is input level monitor of IO buffer which is used for impedance adjustment of OCD.
Address
Bit
15
14
13
Name
R/W
Initial value
X
X
X
Bit field
No.
Name
15-0
(Reserved)
When input value of IO is read, IO driver should be in the OCD adjustment mode.
The following settings are required:
• Bit 0 of IO buffer setting OCD2 register (68h) is set to "1".
• Bit 1 of IO buffer setting OCD2 register (68h) is set to "0".
Remark:
Monitor value is valid only at OCD adjustment.
12
11
10
9
X
X
X
X
Reserved bits.
Write access is ignored.
12
11
10
9
X
X
X
X
Reserved bits.
Write access is ignored.
F300_0000
+ 94
H
H
8
7
6
5
DQSX[15:0]
R
X
X
X
X
Description
) is set to "1".
H
) is set to "0".
H
F300_0000
+ 96
H
H
8
7
6
5
DMX[15:0]
R
X
X
X
X
Description
4
3
2
1
X
X
X
X
4
3
2
1
X
X
X
X
13-25
0
X
0
X
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