Fujitsu MB86R02 Jade-D Hardware Manual page 736

MB86R02 'Jade-D' Hardware Manual V1.64
Bit field
No. Name
15 (Reserved)
14 MSKB
13 MSMD
12 SBFN
11 RHLL
10 ECKM
9 BEXT
8 FRUN
Reserved bits.
The write access is ignored. The read value of these bits is always "0".
Serial output data of invalid transmission frame is set.
For master operation (MSMD = 1), free-running mode (FRUN = 0), and TXENB = 1:
When transmission FIFO is empty at frame synchronous signal output, MSKB is
output to all valid channels of its transmission frame.
For slave operation (MSMD = 0) and TXENB = 1:
When transmission FIFO is empty at frame synchronous signal reception, MSKB is
output to
all valid channels of its transmission frame.
For the case that transmission word length is shorter than the channel length, MSKB is
driven to the rest of bit in transmission channel (channel length -word length.)
Master and slave modes are set.
0 Slave operation
1 Master operation
Sub frame construction (number of sub frame) of the frame is specified.
0 1 sub frame construction (only sub frame 0)
1 2 sub frame construction (sub frame 0 and sub frame 1)
Frame starts from the 0th sub frame
Whether word construction of FIFO is 1 or 2 words is set.
It is considered to be used at protocol, such as I2S and MSB-Justified.
0 32 bit FIFO word is handled as 1 word
1 32 bit FIFO word is handled as 2 words at serial bus with dividing 16 bit each
to low order and high order. They are transferred by serial bus in order of
low order, high order, low order, and high order.
At reception, 2 consecutive words from serial bus is handled as low order and
high order, and they are put in 1 word (32 bit) to write to reception FIFO.
Clock frequency dividing is selected in the master mode.
0 Internal clock (AHB clock) is divided and output
1 External clock (2S_ECLKx pin input) is divided and output
When reception word length is shorter than the word length of FIFO (32 bit when RHLL
is "0", and 16 bit when RHLL is "1"), extension mode of upper bit (word length of FIFO -
reception word length) should be set.
0 Extended by 0
1 Extended by sign bit (for MSB of word is "1", extended by "1" and its "0" is
extended by "0")
Output mode of frame synchronous signal is set.
0 Burst mode
When start bit of OPRREG register is "1", frame synchronous signal is output
according to TXENB, RXENB, and transmission/reception FIFO conditions
1 Free-running mode
When start bit of OPRREG register is "1", frame synchronous signal proceeds
free-running with the set frame rate
When start bit is "0", frame synchronous signal is not output.
Description
27-9