Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
L3ETC (L3 layer Extend Transparency Control)
Register
DisplayBaseAddress + 0x1AC
address
Bit number
31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
L3ETZ
R/W
RW
Initial value
0
This register sets the transparent color for the L3 layer. The 24 bits/pixel transparent color is set
using this register. The lower 15 bits of this register are physically the same as L3TC. Also, L3ETZ
is physically the same as L3TZ.
When L3ETC = 0 and L3EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0
L3ETC (L3 layer Extend Transparent Color)
Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 31
L3EZT (L3 layer Extend Zero Transparency)
Sets handling of color code 0 in L3 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
L4ETC (L4 layer Extend Transparency Control)
Register
DisplayBaseAddress + 0x1B0
address
Bit number
31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
L4ETZ
R/W
RW
Initial value
0
This register sets the transparent color for the L4 layer. This register sets the transparent color for
the L4 layer. When L4ETC = 0 and L4EZT = 0, color 0 is displayed in black (transparent).
Bit 23 to 0
L4ETC (L4 layer Extend Transparent Color)
Sets transparent color code for the L4 layer. In indirect color mode (8 bits/pixel) bits 7 to 0
are used.
Bit 31
L4EZT (L4 layer Extend Zero Transparency)
Sets handling of color code 0 in L4 layer
0
Code 0 as transparency color
1
Code 0 as non-transparency color
18-112
Reserved
R0
0
Reserved
R0
0
L3TEC
RW
L4TEC
RW
Advertisement
Table of Contents
