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MB86R02 'Jade-D' Hardware Manual V1.64
13 DDR2 Controller
This chapter describes function and operation of DDR2 controller (DDR2C).
13.1 Outline
DDR2C adopts AHB bus used in the register access as HOST IF and AXI bus used in the
memory access. Memory IF supports DDR2SDRAM (DDR2-400)*
* Note: MB86R02 'Jade-D' ES1 only supports DDR2-800 memories.
13.2 Features
DDR2C has following features:
a. AHB IF
a) Register access by slave function of AHB IF
b) Register setting contents
a- Operation setting of DDR2C
b- Initialization sequence control (DDR IF macro setting, OCD/ODT setting on DDR2C
side, SDRAM initialization command issue, and SDRAM control setting)
b. AXI IF
a) Storing read/write transactions to internal FIFO by slave function of AHB IF
b) Internal FIFO composition
a- Address FIFO: Depth = 8 ~ 28 (controllable with register setting).
b- Write data FIFO: Depth = 52
c- Read data FIFO: Depth = 62
d- Read control FIFO: Depth = 28
c. DRAM IF
c) 512M bit/256M bit DDR2SDRAM (SSTL18) × 2pcs. (recommended) or 1pc.
(DDR2-400/533/667/800 in compliance with JESD79-2C is used as DDR2-400; in
addition, SDRAM with ODT=50Ω setting is recommended.)
d) Switch of initialization mode and normal operation mode
e) SDRAM usage restriction (AL = 0, CL = 3, WL = 2, BL = 4, Bank = 4)
f) Automatic issuing function of refresh command
g) Max. 166MHz of SDRAM CLK (double edge: 333MHz)
13.3 Limitation
Please note that you should not write to or read from memory using the ARM core when the memory
has been put into self-refresh mode and the clock is turned off. This could cause the system to hang.
13-1
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