Fujitsu MB86R02 Jade-D Hardware Manual page 63

MB86R02 'Jade-D' Hardware Manual V1.64
SYSTEM OSC_MODE0
SYSTEM XRST
SYSTEM VINITHI
UART0 UART_SIN0
UART0 UART_SOUT0
UART0 UART_XCTS0
UART0 UART_XRTS0
UART1 UART_SIN1
UART1 UART_SOUT1
UART2 UART_SIN2
UART2 UART_SOUT2
IO:
A = Analog
D = Digital
I = Input
O = Output
IO = Bidirectional (Input/Output)
Initial state after reset:
H = High
L = Low
HiZ = High-Impedance
1) = First hardware multiplex function
2) = Second hardware multiplex function
3) = Third hardware multiplex function
Type:
PD = Pull-Down
PU = Pull-Up
ST = Schmitt Trigger
CLK = Clock
POD = Pseudo Open-Drain
Tri = Tri-State
MSIO = Multistandard IO (RSDS, LVTTL - no PU or PD for both)
STDIO = Standard IO cell (no PU or PD)
* Note concerning changes for MB86R02 'Jade-D' (ES2)
Please note that the pins described in the above table have been modified in version ES2 of the
MBR02 'Jade-D' device (a pull-up or pull-down has been added). See also Addendum.
D
A7 I oscillator mode 0
D
D6 I System Reset
D5 D I Boot high address
D
AF16 I UART0 serial input
D
AE16 O UART0 serial output
D
AD16 I UART0 Clear to send
D
AC16 O UART0 Request to send
D
AF17 I UART1 serial input
D
AE17 O UART1 serial output
D
AD17 I UART2 serial input
D
AC17 O UART2 serial output
STDIO
-
- ST
- STDIO
1) HiZ 2) H PD *
1) H 2) H STDIO
1) HiZ 2) L PD
1) H 2) L STDIO
HiZ PD
H STDIO
HiZ PD *
H STDIO
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