Modem Status Register (Urtxmsr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
28.6.10

Modem status register (URTxMSR)

ch0：FFFE_1000 + 18h ch1：FFFE_2000 + 18h ch2：FFF5_0000 + 18h
Address
ch3：FFF5_1000 + 18h ch4：FFF4_3000 + 18h ch5：FFF4_4000 + 18h
Bit 31 30 29
Name
R/W R R R
Initial value X X X
Bit 15 14 13
Name
R/W R R R
Initial
valu X X X
e
Bit No. Bit name
31:8 Unused
7 DCD
6 RI
5 DSR
4 CTS
3 DDCD
2 TERI
1 DDSR
0 DCTS
* Bit7:0 = x0h, after reset
Bit7:4 is monitor bit of external pin
28 27 26 25
R R R R
X X X X
12 11 10 9
(Reserved)
R R R R
X X X X
Reserved bit
Data Carrier Detect
Loop = 0: Inversed input signal, XDCD is indicated
Loop = 1: It is equal to OUT2 of MCR
Ring Indicator
Loop = 0: Inversed input signal, XRI is indicated
Loop = 1: It is equal to OUT1 of MCR
Data Set Ready
Loop = 0: Inversed input signal, XDSR is indicated
Loop = 1: It is equal to DTR of MCR
Clear To Send
Loop = 0: Inversed input signal, XCTS is indicated
Loop = 1: It is equal to RTS of MCR
Delta Data Carrier Detect
This bit is set when DCD signal changes after the last reading by CPU. The bit is
reset by reading this register.
Traling Edge of Ring Indicator
This bit is set when RI signal changes from 1 to 0 after the last reading by CPU.
The bit is reset by reading this register.
Delta Data Set Ready
This bit is set when DSR signal changes after the last reading by CPU. The bit is
reset by reading this register.
Delta Clear To Send
This bit is set when CTS signal changes after the last reading by CPU. The bit is
reset by reading this register.
24 23 22 21
(Reserved)
R R R R
X X X X
8 7 6 5
DCD RI DSR CTS
R R R R
X X X X
Function
20 19 18 17
R R R R
X X X X
4 3 2 1
DDCD TERI DDSR DCTS
R R R R
X 0 0 0
28-13
16
R
X
0
R
0