Fujitsu MB86R02 Jade-D Hardware Manual page 13

MB86R02 'Jade-D' Hardware Manual V1.64
14.3 Supply clock ..................................................................................................................... 14-1
14.4 Specification ..................................................................................................................... 14-1
15 DMA Controller (DMAC) .......................................................................................................... 15-1
15.1 Outline .............................................................................................................................. 15-1
15.2 Feature ............................................................................................................................. 15-1
15.3 Block diagram ................................................................................................................... 15-2
15.4 Related pins ...................................................................................................................... 15-3
15.5 Supply clock ..................................................................................................................... 15-3
15.6 Registers .......................................................................................................................... 15-4
15.6.1 Register list ................................................................................................................... 15-4
15.6.2 DMA configuration register (DMACR) .......................................................................... 15-6
15.6.3 DMA configuration A register (DMACAx) ..................................................................... 15-8
15.6.4 DMA configuration B register (DMACBx) ................................................................... 15-11
15.6.5 DMAC source address register (DMACSAx) .............................................................. 15-14
15.6.6 DMAC destination address register (DMACDAx) ....................................................... 15-15
15.7 Operation ........................................................................................................................ 15-16
15.7.1 Transfer modes ........................................................................................................... 15-16
15.7.1.1 Block transfer ....................................................................................................... 15-16
15.7.1.2 Limitations with I2S DMA ..................................................................................... 15-20
15.7.1.3 Burst transfer ....................................................................................................... 15-21
15.7.1.4 Demand transfer .................................................................................................. 15-25
15.7.2 Beat transfer ............................................................................................................... 15-29
15.7.2.1 Normal and Single transfer .................................................................................. 15-29
15.7.2.2 Increment and lap transfer................................................................................... 15-30
15.7.3 Channel priority control ............................................................................................... 15-31
15.7.3.1 Fixed priority ........................................................................................................ 15-31
15.7.3.2 Rotate priority ...................................................................................................... 15-32
15.7.4 Retry, split, and error .................................................................................................. 15-33
15.7.4.1 Retry and split ...................................................................................................... 15-33
15.7.4.2 Error ..................................................................................................................... 15-34
15.8 DMAC Configuration Examples ...................................................................................... 15-35
15.8.1 DMA start in Single channel ....................................................................................... 15-35
15.8.2 DMA start in all channels (in demand transfer mode) ................................................ 15-36
16 Host Interface .......................................................................................................................... 16-1
16.1. Outline .............................................................................................................................. 16-1
16.2. Features ........................................................................................................................... 16-1
16.2.1. Features .................................................................................................................... 16-1
16.2.2. Limitations ................................................................................................................. 16-1
16.3. Function ............................................................................................................................ 16-2
16.3.1. Block Diagram ........................................................................................................... 16-2
16.3.2. SPI Interface.............................................................................................................. 16-2
16.3.2.1. Write Access .......................................................................................................... 16-2
16.3.2.2. Read Access ......................................................................................................... 16-4
16.3.3. Interrupt ..................................................................................................................... 16-6
16.3.3.1. AHB slave module access error response ............................................................ 16-6
16.3.4. Reset Request........................................................................................................... 16-6
16.4. External Interfaces ........................................................................................................... 16-7
16.4.1. Communication Protocols (Timing Diagrams) .......................................................... 16-7
16.4.1.1. SPI protocol stack .................................................................................................. 16-7
16.4.2. Data Formats............................................................................................................. 16-8
16.4.2.1. Host Interface (clock timing and phase) ................................................................ 16-8
16.4.2.2. Reset Frame .......................................................................................................... 16-8