Limitations With I2S Dma - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
15.7.1.2

Limitations with I2S DMA

The I2S unit is only able to handle a subset of the DMA transfer modes that the DMA Controller
supports. For this reason, please take note of the following:

Threshold values in the I2SxINTCNT register (I2S, offset 0x20) must match the BC values of
the respective DMAC register DMACAx (DMACA0 ... DMACA7, various offsets)

Each block matches one transfer request

The selected DMAC transfer mode must be 'Block Transfer' (check the DMACBx registers)

Demand and burst transfer modes can not be used with I2S
In order for DMA transfers to work with the I2S unit, each transfer has to transmit/receive as
many words to/from FIFO as there are valid entries. When DMA has finished, the same setup for
the next transfer has to be configured again in the DMAC and in the I2S module.
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